FIG. 1 shows an example of a prior art memory system 10. In this example, the system resides on a computer motherboard or backplane 12. The system includes a plurality of female electrical connectors 13, which accept memory modules 14 (only one of which is shown here). Each memory module contains a plurality of memory devices 16, typically packaged as discrete integrated circuits (ICs). Memory devices 16 are usually some type of read/write memory, such as RAMs, DRAMs, flash, SRAM, and many other types. ROM devices might also be used. Alternatively, discrete integrated circuits might be assembled into an intermediate level of packaging before being attached to the memory module.
A memory controller 18 is located on motherboard 12. The memory controller communicates with memory modules 14 and memory devices 16 through electrical connectors 13. Memory controller 18 also has an interface (not shown) that communicates with other components on the motherboard, allowing those components to read from and write to memory.
Communications between the controller and the memory modules is by way of a set of signal lines 19, which is typically an electrical bus that extends from the controller, to each of the connectors in parallel, and to the modules. A bus such as this has a plurality of data lines corresponding to data bits of memory words. If a bus has sixteen data lines, the system expects memory modules that generate and accept sixteen parallel data bits.
It is also possible that other signal lines would be present. These additional signal lines could have a different interconnection topology than what is shown for signal lines 19.
The system works with different numbers of memory modules, and with modules having different memory capacities. Also, the specific configuration of memory devices on each module can be varied. A system such as this is normally designed for a specific signal width: for a specified number of signal lines from the controller to the memory modules.
FIG. 2 shows an alternative prior art memory system 30, utilizing point-to-point memory communications rather than a bussed communications structure. The system of FIG. 2 includes a motherboard or backplane 32 and a plurality of female electrical connectors 33 (only two such connectors are shown). Each connector 33 accepts a respective memory module 34. A memory controller 38 supervises and provides communications with the memory modules.
Rather than using bussed signal lines, the system of FIG. 2 includes an independent set of signal lines 36 corresponding to each connector 33. Each set of signal lines extends from memory controller 38 to one of the connectors.
This type of signal line arrangement is referred to as a “point-to-point” configuration, and has several advantages over the bussed structure of FIG. 1, especially in high-speed systems:                Signal transmitters and receivers can be located at ends of transmission lines for optimum configuration of termination circuitry.        No driver handoff between devices is required, which in turn eases device driver output matching requirements, improves efficiency, and simplifies device simulation, characterization, and system-level validation.        Transmitter pre-emphasis equalization circuitry can be simplified, because inter-symbol interference needs to be compensated for only a single receive node.        In some cases, point-to-point interconnects are shorter than bussed interconnects, allowing reduced signal attenuation, reduced flight time, simplified delay matching, and fewer impedance discontinuities.        The memory controller can integrate clock control or calibration circuitry, providing opportunities for system level cost reduction.        